(A) Field of the Invention
The present invention relates to an arithmetic circuit, and more particularly, to an arithmetic circuit for matrix and scalar multiplication.
(B) Description of the Related Art
As usage of the Internet continues to grow, the demand for security has become the priority issue in network communication. The realizations of information security algorithms can be roughly categorized into two types:
software-based and hardware-based implementations. The software-based implementation utilizes a processing unit to execute the calculation of the cryptographic algorithms. However, when traffic on the network increases, the processing unit will perform poorly as the capacity thereof will mainly occupied by instructions related to the network packets. The performance downgrade is much alleviated in hardware-based implementation, since there is a hardware circuit dedicated to the calculation of the cryptographic algorithms. Therefore, in high rate network communication, most systems are implemented hardware-wise.
Cryptography can be categorized into two types based on the key used in the algorithm: symmetric systems and asymmetric systems. Symmetric systems use the same key during the encryption and decryption process, while asymmetric systems use different ones. Advanced Encryption Standard (AES), which is a new symmetric system announced by the National Institute of Standards and Technology in 2001, requires matrix multiplications during the encryption and decryption process. Meanwhile, Elliptic Curve Cryptography (ECC) and Rivest-Shamir-Adelman (RSA) algorithms, both asymmetric systems, require scalar multiplications during the encryption and decryption process. These systems are used widely in cryptography systems, so an integrated design that can support AES RSA, and ECC is necessary. Therefore, it is necessary to design a multiplication circuit supporting both matrix and scalar multiplications.